Recently, energy saving in all electric products has been proposed in view of environmental protection, and in particular, it has become an important problem that recent power source devices should require reduction in power consumption during the standby condition. In addition, with increase of mobile electric equipments such as cellular phones late years, power source devices are necessary which have a chargeable battery and are safe under any loaded condition including an abnormal condition.
A prior art DC power source device shown in FIG. 6 comprises a primary winding 3 of a transformer 2 and a switching element or MOS-FET 5 connected in series to a DC power supply 1; a rectifying smoother 6 connected to a secondary winding 4 of transformer 2 for supplying DC output power to a load 50; and a control circuit 9 for controlling turning-on and -off of MOS-FET 5 in response to the level of DC output supplied to load 50. Rectifying smoother 6 comprises a rectifying diode 7 connected to secondary winding 4 and a smoothing capacitor 8 connected to rectifying diode 7 to supply DC output to load 50 through DC output terminals 29 and 30.
Control circuit 9 comprises a voltage stabilizer 10 for producing control signals of constant or regulated voltage to control the on-off period of MOS-FET 5 in order to make DC output voltage VO to load 50 stabilize to a constant value V2; a current controller 11 for producing current control signals to control the on-off period of MOS-FET 5 in order to make DC output current IO settle on a constant value when DC output current IO supplied to load 50 exceeds a rated value IOMAX; a shunt regulator 24 as a reference voltage generator for producing a reference voltage VREF; a light emitter 26 of a photo-coupler 25 driven by logical sum signals of each output from voltage stabilizer 10 and current controller 11 for radiating a light output; a light receiver 27 of photo-coupler 25 for passing therethrough electric current the amount of which changes in proportion to an amount of light output radiated from light emitter 26; and a PWM controller 28 for supplying a gate terminal of MOS-FET 5 with drive signals VG of variable pulse width in response to the amount of electric current through light receiver 27 of photo-coupler 25. Shunt regulator 24 is driven by output current ISH from rectifying smoother 6 supplied through a bias resistor 23 to produce a reference voltage VREF for regulating a reference value of output voltage VO. Shunt regulator 24 may comprise, for example, a well-known IC (integrated circuit) for reference voltage such as TL431. Resistance value of bias resistor 23 is determined to supply shunt regulator 24 with drive current ISH of a necessary minimum value when DC output voltage VO is of the constant value V2. PWM controller 28 produces drive signals VG of wide and narrow pulse width when respectively small and large amount of electric current flows through light receiver 27 of photo-coupler 25.
Voltage stabilizer 10 comprises detective resistors 12 and 13 connected between output terminals of rectifying smoother 6 for dividing DC output voltage VO to load 50 into a desirable step-down level; and a voltage-controlling operational amplifier 14 which has an inverted input terminal for receiving a first divided voltage on a first junction between detective resistors 12 and 13 and a non-inverted input terminal for receiving a reference voltage VREF of shunt regulator 24. Voltage-controlling operational amplifier 14 compares divided voltage on junction between detective resistors 12 and 13 and reference voltage VREF of shunt regulator 24 to produce an error voltage between the divided and reference voltages as a control signal for constant voltage. Output terminal of voltage-controlling operational amplifier 14 is connected to light emitter 26 through a resistor 15 and a diode 16. Current controller 11 comprises a current detecting resistor 17 as an output current detection means connected to a negative output line of rectifying smoother 6 for detecting DC output current IO through load 50 as a voltage corresponding to output current IO; parting resistors 18 and 19 connected to two terminals of shunt regulator 24 for dividing reference voltage VREF from shunt regulator 24 into a second divided voltage on second junction between parting resistors 18 and 19 so that the second divided voltage provides a reference voltage VR1 for regulating the rated current value IOMAX; and a current-controlling operational amplifier 20 which has a non-inverted terminal for receiving detection signals from current detecting resistor 17 and an inverted terminal for receiving reference voltage VR1 on second junction between parting resisters 18 and 19. Output terminal of current-controlling operational amplifier 20 is connected to light emitter 26 through a resistor 21 and a diode 22. Current-controlling operational amplifier 20 compares detection signal from current detecting resistor 17 and reference voltage VR1 to produce an error voltage therebetween as a constant current control signal. Voltage control operational amplifier 14 produces control signals for constant voltage which thereby causes electric current to flow through a resistor 15, a diode 16 and light emitter 26. Current control operational amplifier 20 produces control signals for constant current which thereby causes electric current to flow through a resistor 21, a diode 22 and light emitter 26. Optical output signals from light emitter 26 of photo-coupler 25 are controlled by a composite logical sum signal formed by constant voltage-current control signals from voltage and current control operational amplifiers 14 and 20.
Light emitter 26 of photo-coupler 25 produces a light output which is received by light receiver 27 to control electric current flowing through light receiver 27 to be proportional to an amount of light output from light emitter 26. PWM controller 28 modulates the pulse width of drive signals VG based on a value of electric current flowing through light receiver 27 of photo-coupler 25 and provides gate terminal of MOS-FET 5 with the pulse width-modulated drive signal VG. Resistors 15, 21, diodes 16, 22, photo-coupler 25 and PWM controller 28 form a drive signal generator. In this way, control circuit 9 controls the on-off period of MOS-FET 5 in response to DC output voltage VO and DC output current IO supplied to load 50 to always supply such stabilized DC output to load 50.
In operation of the DC power source device shown in FIG. 6, PWM controller 28 of control circuit 9 forwards drive signals VG to gate terminal of MOS-FET 5 to alternately turn MOS-FET 5 on and off so that DC input voltage is applied from DC power supply 1 to primary winding 3 of transformer 2 and MOS-FET 5 to cause electric current of high frequency to run through primary winding 3 and MOS-FET 5. Electric current of high frequency through primary winding 3 induces on secondary winding 4 high frequency voltage which is then rectified and smoothed by rectifying diode 7 and smoothing capacitor 8 of rectifying smoother 6, and converted into DC output voltage VO to load 50 through DC output terminals 29, 30.
When DC output current IO equal to or less than a rated value IOMAX is supplied to load 50 through DC output terminals 29 and 30, voltage stabilizer 10 of control circuit 9 operates to control DC output voltage VO toward load 50 to a constant value V2 as shown by a solid line A in FIG. 7. Under such a normal operating condition, DC output voltage VO between DC output terminals 29 and 30 is split to first junction voltage between detective resistors 12 and 13 so that voltage control operational amplifier 14 compares first junction voltage on the inverted input terminal with reference voltage VREF on the non-inverted input terminal from shunt regulator 24 to generate an error voltage between these compared voltages from output terminal of voltage control operational amplifier 14. Accordingly, when first junction voltage divided from DC output voltage VO is lower than reference voltage VREF from shunt regulator 24, voltage control operational amplifier 14 produces a positive error voltage to reduce an amount of light output from light emitter 26 of photo-coupler 25, decreasing electric current through light receiver 27. With declination of electric current through light receiver 27, PWM controller 28 operates to widen on-pulse width or time span of drive signals VG and provide them for MOS-FET 5 which therefore is turned on for a longer time. To the contrary, when first junction voltage of DC output voltage VO is greater than reference voltage VREF from shunt regulator 24, PWM controller 28 performs an opposite operation from the above-mentioned to shorten the on-period of MOS-FET 5. Thus, as shown by solid line A, DC output voltage VO can be adjusted toward a constant value V2 to supply load 50 with DC output power of constant voltage through DC output terminals 29 and 30.
In case DC output current IO through load 50 is greater than rate value VOMAX as in the overloaded condition, current control circuit 11 of control circuit 9 operates to control DC output current IO to the constant rated value IOMAX as shown by solid line B in FIG. 7. Here, as DC output current IO toward load 50 flows through detecting resistor 17 which picks out DC output current IO as a corresponding voltage value thereto. On the other hand, parting resistors 18 and 19 split reference voltage VREF from shunt regulator 24 to produce on second junction between parting resistors 18 and 19 reference voltage VR1 used to regulate DC output current IO toward the rated value IOMAX. Sensed voltage by detecting resistor 17 is input to inverted input terminal of current control operational amplifier 20 which compares sensed voltage from detecting resistor 17 with reference voltage VR1 on non-inverted terminal of operational amplifier 20 from second junction between parting resistors 18 and 19 so that operational amplifier 20 produces an error voltage between sensed voltage and reference voltage VR1 from output terminal. Error voltage from output terminal of operational amplifier 20 provides a control signal for constant current which flows through light emitter 26, diode 22 and resistor 21 to form a logical sum signal in cooperation with a control signal for constant voltage produced from voltage control operational amplifier 14. Accordingly, when DC output current IO toward load 50 exceeds the rated value IOMAX so that detection voltage by detecting resistor 17 is above reference voltage VR1 on second junction between parting resistors 18 and 19, current control operational amplifier 20 generates a negative error voltage to reduce the on-period of MOS-FET 5. Consequently, DC output voltage VO rapidly drops while DC output current IO through load 50 is maintained on a constant level IOMAX as shown by solid line B in FIG. 7, indicating the constant current output characteristics. A typical example of such a DC power source device is disclosed by Japanese Patent No. 3,099,763.
Meanwhile, DC power source device shown in FIG. 6 is defective in that it cannot supply shunt regulator 24 with minimum drive current ISH necessary to keep reference voltage VREF on a constant level when DC output voltage VO declines to a lower voltage VI because resistance value of bias resistor 23 is determined to supply shunt regulator 24 with drive current ISH of a necessary minimum value when DC output voltage VO is on the constant value V2. As a result, when DC output voltage VO drops as shown by solid line B in FIG. 7, shunt regulator 24 fluctuates reference voltage VREF, and therefore, disadvantageously changes DC output current IO. On the contrary, if bias resistor 23 is set to a low resistance value to supply shunt regulator 24 with drive current ISH of necessary minimum value when DC output voltage VO falls to lower voltage V1, a large electric current runs through bias resistor 23 when DC output voltage VO is of constant value V2, thereby inconveniently causing increase in power loss across bias resistor 23. As power loss across bias resistor 23 is indicated by seeking the square of potential difference between voltages V1 and V2 and then dividing the square by resistance value of bias resistor 23, the power loss increases with the greater difference between voltages V1 and V2. During the load standby mode such as under the unloaded or light-loaded condition, the power source device increases the ratio of power loss across bias resistor 23 to the whole power loss so that increased power loss with bias resistor 23 is a serious hindrance against improvement in conversion efficiency during the load standby mode. In this manner, control circuit 9 unfavorably and rapidly increases a rate of consumed power in the load standby mode.
It is therefore an object of the present invention to provide a DC power source device which supplies a reference voltage source with necessary minimum drive current in case of the lowered output voltage, and controls drive current for the reference voltage source to a necessary minimum level in case of the rated output to reduce electric power consumed by the control circuit in the load standby mode such as under unloaded or light-loaded condition.